The basic delta-sigma architecture is one where an analog input value is summed with a feedback value (which is often implemented as a voltage) to produce an error difference that is integrated and subsequently quantized into discrete values by an ADC (Analog to Digital Converter). A DAC (Digital to Analog Converter) driven by the ADC produces the feedback value. When the feedback value equals the input value the integrator output stops ramping, but typically hunts on either side of the true point of loop balance, owing to finite resolution of the ADC-DAC combination (i.e., the feedback value is quantized, but the input value is not, so exact cancellation is unlikely). Typically, the ADC and the DAC operate at the same rate, and that rate corresponds to a bandwidth that is much higher than a limited bandwidth with which the applied input is allowed to vary. A digital filter is responsive to the sequence of quantized values from the ADC; the digital filtering averages out the hunting to produce a result that corresponds (perhaps after some brief delay needed for the loop to balance, or nearly so) to a recent value of the bandwidth limited input. If desired, the ADC values may be further processed to produce a digital output that represents another measure of the applied analog input value (e.g., its Root Mean Squared value).
The basic delta-sigma architecture just described is well known, and that basic architecture and variants thereof have been used in a variety of different applications, as described in the literature. See, in particular, OVERSAMPLING DELTA-SIGMA DATA CONVERTERS Theory, Design and Simulation, edited by Steven R. Norsworthy, Richard Schreier and Gabor C. Temes, published in 1997 by the IEEE Press (ISBN 0-7803-1045-4).
There have been a number of improvements or extensions of the basic delta-sigma technique over the years since a delta modulator was first proposed in 1954 by C. C. Cutler (see U.S. Pat. No. 2,927,962) and a sigma improvement thereto was proposed in 1962 by Inose, Yasuda and Murakami. Among these are various way to incorporate, by nesting or by cascading, one instance of the architecture with another (‘higher order loops’) with the goal of improved performance.
At present, the delta-sigma architecture is the highest accuracy architecture known for an ADC. Other ADC architectures can run faster, but the delta-sigma architecture has accuracy and linearity that depend chiefly on just the DAC. This can be appreciated if one considers that it is the difference between the actual input and the replica thereof produced by the DAC that is the origin of the feedback that drives the loop to balance (where ‘balance’ includes the notion of continuous hunting that ‘balances over time’ about the correct answer). Any non-linearity in the ADC, or offset or non-linearity in the integrator is construed by the loop as just further error to be nulled out through hunting. We may thus think of the hunting as having a component that corresponds to quantization issues arising from finite resolution in the ADC and the DAC, and other components that appear in whatever degree is needed to get the loop to balance (through hunting). Almost by definition, when the loop is thus balanced, the digital input to the DAC has GOT to represent the input to the degree we can detect error in the difference between the actual input and the feedback. That is why the integrator is such a powerful actor in the delta-sigma architecture: over time even very small errors (think: degrees of imbalance) are accumulated into actionable quantities that drive the hunting process and null themselves out.
Now, we believe that the DAC described in the incorporated '241 B2 Patent is at present, anyway, about as good as they come for use in a delta-sigma converter. It is a pulse width/duty cycle affair designed to exhibit very stable transition times and large voltage swings. In this application we seek ways to operate a delta-sigma ADC with the best linearity and the greatest precision obtainable in a commercially produced DVM (Digital Volt Meter). We are also mindful that many of the ‘higher order loops’ described in the literature have stability problems (say, for example, under certain conditions the hunting behavior becomes a willful and independent ‘self-winding oscillator’ rather than a mechanism that tracks the input and nulls out errors).
In many respects the delta-sigma architecture resembles a sampled control loop, and the needed integration can be provided by either a discrete (sampled) or continuous integrator mechanism. Some instances of the delta-sigma conversion technique intended for consumer or other high volume/low cost applications have applied the techniques of Integrated Circuit (IC) design to produce an entire delta-sigma converter within a single chip. As a part of these efforts a continuous integrator is often avoided in favor of a switched capacitor integration technique that produces an output based solely on samples taken at the discrete points in time when the DAC and ADC make their decisions as to what their outputs are to be. (For steady state DC inputs the switched capacitor integrator produces what the output of an actual continuous integrator would be if it were used instead.) And, since a switched capacitor integrator uses sampling techniques to enforce the notion of discrete points in time, an AC input is automatically quantized into a series of discrete steps (any change in the AC input during the interim between loop decisions is simply not seen and is ignored). However, such switched capacitor integration techniques are subject to various error mechanisms that limit the precision of the delta-sigma converters of which they are a part, even for DC inputs. At present, a delta-sigma ADC of the highest precision must use an actual continuous time (think genuine analog) integrator.
Furthermore, if the loop decision time for the feedback in the delta-sigma architecture is short, say on the order of a microsecond, then we are tempted to use the delta-sigma technique to generate a sequence of digital values that represent an AC signal having a bandwidth of up to 100 KHz, or so. Unfortunately, the genuine analog integrator needed to obtain high precision for DC creates a frequency related error (in the integrated loop error signal) that increases as frequency gets higher, and degrades loop performance. Thus, the use of a continuous integrator with an AC input is another area of delta-sigma behavior that is susceptible of improvement.
It turns out that using an actual continuous integrator performs ‘extra’ integration for AC signals that adds an additional component to the hunting. (It is ‘extra’ only in the sense that the AC input continues to change in the interim between loop decision cycles for quantization and feedback adjustment, and the continuous integrator sees that movement and incorporates it into the integrated result.) In one sense these additional movements in the error signal constitute unwanted components that adversely affect the output (they arise, as far as a quantized view of the loop's universe is concerned, ‘out of nowhere’).
It would be desirable if there were a way to eliminate the error related to input frequency produced in a delta-sigma converter that is otherwise precision and that uses a continuous time genuine analog integrator.